|
No. |
Title |
Publication |
Down
|
| Authors |
|
134
|
An Attachable ECG Sensor Bandage with Planar-Fashionable Circuit Board |
ISWC
2009 |
|
| Jerald Yoo, Long Yan, Seulki Lee, Hyejung Kim, Binhee Kim, and Hoi-Jun Yoo |
|
133
|
A 118.4GB/s Multi-Casting Network-on-Chip for Real-Time Object Recognition Processor |
ESSCIRC
2009 |
|
| Joo-Young Kim, Kwanho Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, and Hoi-Jun Yoo |
|
132
|
A 60fps 496mW Multi-Object Recognition Processor with Workload-Aware Dynamic Power Management |
ISLPED
2009 |
|
| Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, and Hoi-Jun Yoo |
|
131
|
A Dynamic Real-time Capacitor Compensated Inductive Coupling Transceiver for Wearable Body Sensor Network |
SOVC
2009 |
|
| Seulki Lee, Jerald Yoo, Hyejung Kim,
and Hoi-Jun Yoo
|
|
130
|
A 490uW Fully MICS Compatible FSK Transceiver for Implantable Devices |
SOVC
2009 |
|
| Joonsung Bae, Namjun Cho, and Hoi-Jun Yoo
|
|
129
|
A 22.8GOPS 2.83mW Neuro-fuzzy Object Detection Engine for Fast Multi-object Recognition |
SOVC
2009 |
|
| Minsu Kim, Joo-Young Kim, Seungjin Lee,Jinwook Oh, and Hoi-Jun Yoo
|
|
128
|
A Wearable Fabric Computer by Planar-Fashionable Circuit Board Technique |
BSN
2009 |
|
| Hyejung Kim, Yongsang Kim, Binhee Kim, and Hoi-Jun Yoo |
|
127
|
A Wearable Inductor Channel Design for Blood Pressure Monitoring System in Daily Life
|
Pervasive Health 2009 |
|
| Seulki Lee, Jerald Yoo, and Hoi-Jun Yoo
|
|
126
|
An Energy Efficient Real-Time Object Recognition Processor with Neuro-Fuzzy
Controlled Workload-aware Task Pipelining |
CoolChips 2009 |
|
| Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Jeong-Ho Woo,
and Hoi-Jun Yoo |
|
125
|
A 10.8mW Body-Channel-Communication/MICS Dual-Band Transceiver for a Unified
Body-Sensor-Network Controller |
ISSCC 2009 |
|
| Namjun Cho, Joonsung Bae, and Hoi-Jun Yoo |
|
124
|
A 5.2mW Self-Configured Wearable Body Sensor Network Controller and a 12¥ìW
54.9% Efficiency Wirelessly Powered Sensor for Continuous Health Monitoring System |
ISSCC 2009 |
 |
| Jerald Yoo, Long Yan, Seulki Lee , Yongsang Kim, Hyejung Kim, Binhee Kim, and Hoi-Jun Yoo |
|
123
|
A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor with Bio-Inspired
Neural Perception Engine |
ISSCC 2009 |
|
| Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Sejong Oh, Jeong-Ho Woo, Donghyun Kim, and Hoi-Jun Yoo |
|
122
|
An Interference-Resilient Body Channel Transceiver for Wearable Body Sensor Network
|
BioCAS 2008 |
|
| Namjun Cho, Joonsung Bae, and Hoi-Jun Yoo |
|
121
|
A Two-Electrode 2.88nJ/Conversion Biopotential Acquisition System for Portable Healthcare Device |
A-SSCC 2008 |
|
| Long Yan, Namjun Cho, Jerald Yoo, Binhee Kim, and Hoi-Jun Yoo |
|
120
|
A Low Energy Bio Sensor Node Processor for Continuous Healthcare Monitoring System |
A-SSCC 2008 |
|
| Hyejung Kim, Yongsang Kim , and Hoi-Jun Yoo |
|
119
|
A 1.12pJ/b Resonance Compensated Inductive Transceiver with a Fault-Tolerant Network Controller for Wearable Body Sensor Networks |
A-SSCC 2008 |
|
| Jerald Yoo, Seulki Lee , and Hoi-Jun Yoo |
|
118
|
A 76.8 GB/s 46 mW Low-latency Network-on-Chip for Real-time Object Recognition Processor |
A-SSCC 2008 |
|
| Kwanho Kim, Joo-Young Kim, Seungjin Lee, Minsu Kim, and Hoi-Jun Yoo |
|
117
|
A 66fps 38mW Nearest Neighbor Matching Processor with Hierarchical VQ Algorithm for Real-Time Object Recognition |
A-SSCC 2008 |
|
| Joo-Young Kim, Kwanho Kim, Seunjin Lee, Minsu Kim, and Hoi-Jun Yoo |
|
116
|
A 211 GOPS/W Dual-Mode Real-Time Object Recognition Processor with Network-on-Chip
|
ESSCIRC 2008 |
|
| Kwanho Kim,
Joo-Young Kim, Seungjin Lee, Minsu Kim, and Hoi-Jun Yoo |
|
115
|
A Low Cost Quadratic Level ECG Compression Algorithm and Its Hardware Optimization for Body Sensor Network System
|
EMBC 2008 |
|
| Hyejung Kim, Yongsang Kim, and Hoi-Jun Yoo |
|
114
|
Autonomous Gain Verification Algorithm for a Dual Mode Digital Hearing Aid Chip
|
EMBC 2008 |
|
| Sunyoung Kim , Long Yan, Minsu Kim, Joonsung Bae and Hoi-Jun Yoo |
|
113
|
The Brain Mimicking Visual Attention Engine: An 80x60 Digital Cellular Neural Network for Rapid Global Feature Extraction |
SOVC 2008 |
|
| Seungjin Lee, Kwanho Kim, Minsu Kim, Joo-Young Kim, and Hoi-Jun Yoo |
|
112
|
Vision Platform for Mobile Intelligent Robots Based on 81.6 GOPS Objects Recognition Processor |
DAC 2008 |
|
| Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, and Hoi-Jun Yoo |
|
111
|
A Healthcare Monitoring System with Wireless Woven Inductor Channels for Body Sensor Network |
BSN 2008 |
|
| Seulki Lee, Jerald Yoo, and Hoi-Jun Yoo |
|
110
|
A 0.6pJ/b 3Gb/s/ch Transceiver in 0.18 um CMOS for 10mm On-chip interconnects |
ISCAS 2008 |
|
| Joonsung Bae, Joo-Young Kim, and Hoi-Jun Yoo |
|
109
|
A 6.3nJ/op Low Energy 160-bit Modulo-Multiplier
for Elliptic Curve Cryptography Processor |
ISCAS 2008
|
|
| Hyejung Kim, Yongsang Kim, and Hoi-Jun Yoo |
|
108
|
A 200Mbps 0.02nJ/b dual-mode inductive coupling
transceiver for cm-range interconnection |
ISCAS 2008
|
|
| Seulki Lee, Jerald Yoo, and Hoi-Jun Yoo |
|
107
|
Analysis of Body Sensor Network Using Human Body as
the Channel |
BodyNets 2008
|
|
| Jerald Yoo, Namjun Cho, and Hoi-Jun Yoo |
|
106
|
A 60kb/s-to-10Mb/s, 0.37nJ/b Adaptive-Frequency-Hopping Transceiver for Body-Area Network |
ISSCC 2008
|
|
| Namjun Cho, Jeabin Lee, Long Yan, Joonsung Bae, Sunyoung Kim, and Hoi-Jun Yoo |
|
105
|
A 1.12mW Continuous Healthcare Monitor Chip Integrated on A Planar-Fashionable Circuit Board |
ISSCC 2008
|
|
| Hyejung Kim, Youngsang Kim, Young-se Kwon, and Hoi-Jun Yoo |
|
104
|
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual Attention Engine |
ISSCC 2008 |
|
| Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Donghyun Kim, Jeong-Ho Woo, and Hoi-Jun Yoo |
|
103
|
A 195mW, 9.1MVertices/s Fully Programmable 3D Graphics Processor for Low Power Mobile Devices |
A-SSCC 2007
|
|
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongchel Jeong, Euljoo Jeong, Suk-Joong Lee, and Hoi-Jun Yoo |
|
102
|
Implementation of Memory-Centric NoC for 81.6 GOPS Object Recognitiion Processor |
A-SSCC 2007
|
|
| Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, and Hoi-Jun Yoo |
|
101
|
Bitwise Competition Logic for Compact Digital Comparator |
A-SSCC 2007
|
|
| Joo-Young Kim, and Hoi-Jun Yoo |
|
100
|
Dynamic Voltage and Frequency Scaling (DVFS) Scheme for Multi-Domains Power Management |
A-SSCC 2007
|
|
| Jeabin Lee, Byeong-Gyu Nam, and Hoi-Jun Yoo |
|
99
|
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory |
CICC 2007
|
|
| Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, and Hoi-Jun Yoo |
|
98
|
A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model |
CICC 2007
|
|
| Sunyoung Kim, Seung-Jin Lee, Namjun Cho, Seong-Jun Song and Hoi-Jun Yoo |
|
97
|
An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM
|
CICC 2007
|
|
| Hyejung Kim, Kyomin Sohn, Jerald Yoo and Hoi-Jun Yoo |
|
96
|
A Low-Power Vector Processor Using Logarithmic Arithmetic for Handheld 3D Graphics Systems |
ESSCIRC 2007
|
|
| Byeong-Gyu Nam and Hoi-Jun Yoo |
|
95
|
Visual Image Processing RAM for Fast 2-D Data Location Search |
ESSCIRC 2007
|
|
| Joo-Young Kim , Donghyun Kim, Seung-Jin Lee, Kwanho Kim, Sunghyun Jeon and Hoi-Jun Yoo |
|
94
|
A Low Power Multimedia SoC with Fully Programmable 3D Graphics and MPEG4/H.264/JPEG for Mobile Devices |
ISLPED 2007
|
|
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee and Hoi-Jun Yoo |
|
93
|
The Reference Ear Modeling Method for Internally Feedback Controlled Digital Hearing Aid Chip |
EMBC
2007
|
|
| Sunyoung Kim, Seung-Jin Lee, Namjun Cho, Seong-Jun Song and Hoi-Jun Yoo |
|
92
|
Energy-Efficient Human Body Communication Receiver Chipset Using Wideband Signaling Scheme |
EMBC 2007
|
|
| Seong-Jun Song, Namjun Cho, Sunyoung Kim and Hoi-Jun Yoo |
|
91
|
Dual Threshold Preamplifier and Multi-Channel DSP for Human Factored Digital Hearing Aid Chip |
SOVC 2007 |
 |
| Sunyoung Kim, Seung-Jin Lee, Namjun Cho, Seong-Jun Song and Hoi-Jun Yoo |
|
90
|
A 152mW Mobile Multimedia SoC with Fully Programmable 3D Graphics and MPEG4/H.264/JPEG |
SOVC 2007 |
 |
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee and Hoi-Jun Yoo |
|
89
|
Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM |
SOVC 2007 |
 |
| Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo,
Seung-Jin Lee, Woo-Yeong Cho, Bo-Tak Lim, Byung-Gil Choi, Chang-Sik Kim, Choong-Keun Kwak, Chang-Hyun Kim and Hoi-Jun Yoo |
|
88
|
A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling |
ISCAS
2007 |
 |
| Jeabin Lee, Byeong-Gyu Nam, Seong-Jun Song, Namjun Cho and Hoi-Jun Yoo |
|
87
|
A Low Power Digital Signal Processor with Adaptive
Band Activation for Digital Hearing Aid Chip |
ISCAS
2007 |
 |
| Seung Jin Lee, Sunyoung Kim, and Hoi-Jun Yoo |
|
86
|
Solutions
for Real Chip Implementation Issues
of NoC and Their Application to Memory-Centric
NoC |
NOCS
2007 |
 |
| Donghyun
Kim, Kwanho Kim, Joo-Young Kim, Seungjin
Lee, and Hoi-Jun Yoo |
|
85
|
Cost-efficient
Network-on-Chip Design Using Traffic
Monitoring System |
DATE W/S
2007 |
 |
| Kwanho
Kim, Donghyun Kim, Kangmin Lee, and
Hoi-Jun Yoo |
|
84
|
A
Low Power Compression Processor for
Body Sensor Network System |
BSN
2007 |
 |
| Hyejung
Kim, Sungdae Choi, and Hoi-Jun Yoo |
|
83
|
Low
Energy On-Body Communication for BSN |
BSN
2007 |
 |
| Hoi-Jun
Yoo, Seong-Jun Song, Namjun Cho and
Hye-Jeong Kim |
|
82
|
A
152mW/195mW Multimedia Processor with
Fully Programmable 3D Graphics
and MPEG/H.264/JPEG for Handheld Devices |
DAC
2007 |
¡¡
|
| Jeong-Ho
Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol
Jeong, Euljoo Jeong, Suk Joong Lee and
Hoi-Jun Yoo |
|
81
|
A
Fully Integrated Digital Hearing-Aid
Chip with Human-Factors Considerations |
ISSCC
2007 |
 |
| Sunyoung
Kim, Seung Jin Lee, Namjun Cho, Seong-Jun
Song and Hoi-Jun Yoo |
|
80
|
A
0.9V 2.6mW Body-Coupled Scalable PHY
Transceiver for Body Sensor Applications |
ISSCC
2007 |
 |
| Seong-Jun
Song, Namjun Cho, Sunyoung Kim, Jerald
Yoo, Sungdae Choi and Hoi-Jun Yoo |
|
79
|
A
52.4mW 3D Graphics Processor with 141Mvertices/s
Vertex Shader and 3 Power Domains
of Dynamic Voltage and Frequency Scaling |
ISSCC
2007 |
 |
| Byeong-Gyu
Nam, Jeabin Lee, Kwanho Kim, Seung Jin
Lee and Hoi-Jun Yoo |
|
78
|
Clearphone
: A 0.9 V 96 µW Digital Hearing
Aid System |
BIOCAS
2006 |
 |
| Sunyoung
Kim, Namjun Cho, Seong-Jun Song, Donghyun
Kim, Kwanho Kim and Hoi-Jun Yoo |
|
77
|
A
Low Power 16-bit RISC with Lossless
Compression Accelerator for Body
Sensor Network System |
A-SSCC
2006 |
 |
| Hyejung
Kim, Sungdae Choi, and Hoi-Jun Yoo |
|
76
|
A
TCAM-based Periodic Event Generator
for Multi-Node Management in
the Body Sensor Network |
A-SSCC
2006 |
 |
| Sungdae
Choi, Kyomin Sohn, Jooyoung Kim, Jerald
Yoo, and Hoi-Jun Yoo |
|
75
|
A
0.6-V, 6.8-uW Embedded SRAM for Ultra-low
Power SoC |
A-SSCC
2006 |
 |
| Kyomin
Sohn, Sungdae Choi, Jeong-Ho Woo, Jooyoung
Kim, and Hoi-Jun Yoo |
|
74
|
A
210MHz, 15mW Unified Vector and Transcendental
Function Unit for Handheld 3-D
Graphics Systems |
A-SSCC
2006 |
 |
| Byeong-Gyu
Nam, Hyejung Kim, and Hoi-Jun Yoo |
|
73
|
A
Low-power Star-topology Body Area Network
Controller for Periodic Data
Monitoring Around and Inside the Human
Body |
ISWC
2006 |
 |
| Sungdae
Choi, Seong-Jun Song, Kyomin Sohn, Hyejung
Kim, Jooyoung Kim, Jerald Yoo, and Hoi-Jun
Yoo |
|
72
|
Low
Power Wearable Audio Player Using Human
Body Communications |
ISWC
2006 |
 |
| Seong-Jun
Song, Seung Jin Lee, Namjun Cho, and
Hoi-Jun Yoo |
|
71
|
A
24.2-uW Dual-Mode Human Body Communication
Controller for Body Sensor Network |
ESSCIRC
2006 |
 |
| Sungdae
Choi, Seong-Jun Song, Kyomin Sohn, Hyejung
Kim, Jooyoung Kim, Namjun Cho, Jeong-Ho
Woo, Jerald Yoo and Hoi-Jun Yoo |
|
70
|
A
4.8-mW 10-Mb/s Wideband Signaling Receiver
Analog Front-End for Human Body
Communications |
ESSCIRC
2006 |
 |
| Seong-Jun
Song, Namjun Cho, Sunyoung Kim, and
Hoi-Jun Yoo |
|
69
|
A
Sub 1V 96 uW Fully Operational Digital
Hearing Aid Chip With Internal
Status Controller |
ESSCIRC
2006 |
 |
| Sunyoung
Kim, Namjun Cho, Seong-Jun Song, Donghyun
Kim, Kwanho Kim and Hoi-Jun Yoo |
|
68
|
A
Multi-Nodes Human Body Communication
Sensor Network Control Processor |
CICC
2006 |
 |
| Sungdae
Choi, Seong-Jun Song, Kyomin Sohn, Hyejung
Kim, Jooyoung Kim, Namjun Cho, Jeong-Ho
Woo, Jerald Yoo and Hoi-Jun Yoo |
|
67
|
A
Low-Power Unified Arithmetic Unit for
Programmable Handheld 3-D Graphics
Systems |
CICC
2006 |
 |
| Byeong-Gyu
Nam, Hyejung Kim, and Hoi-Jun Yoo |
|
66
|
A
0.9-V 96-¥ìW Digital Hearing Aid Chip
with Heterogeneous ¥Ò-¥Ä DAC |
SOVC
2006 |
 |
| Sunyoung
Kim, Namjun Cho, Seong-Jun Song, Donghyun
Kim, Kwanho Kim and Hoi-Jun Yoo |
|
65
|
A
10-uW Digital Signal Processor with
Adaptive-SNR Monitoring for a
Sub-1V Digital Hearing Aid |
ISCAS
2006 |
 |
| Jerald
Yoo, Sunyoung Kim, Namjun Cho, Seong-Jun
Song, and Hoi-Jun Yoo |
|
64
|
A
372ps 64-bit Adder using Fast Pull-up
Logic in 0.18-um CMOS |
ISCAS
2006 |
 |
| Jooyoung
Kim, Kangmin Lee and Hoi-Jun Yoo |
|
63
|
Design
and Test of Fixed-point Multimedia Co-processor
for Mobile Applications |
DATE
2006 |
 |
| Ju-Ho
Sohn, Jeong-Ho Woo, Jerald Yoo and Hoi-Jun
Yoo |
|
62
|
A
2Mb/s Wideband Pulse Transceiver with
Direct-Coupled Interface for
Human Body Communications |
ISSCC
2006 |
 |
| Seong-Jun
Song, Namjun Cho, Sunyoung Kim, Jerald
Yoo and Hoi-Jun Yoo |
|
61
|
A
231MHz, 2.18mW 32-bit Logarithmic Arithmetic
Unit for Fixed-Point 3D Graphics
System |
A-SSCC
2005 |
 |
| Hyejung
Kim, Byeong-Gyu Nam, Ju-Ho Sohn and
Hoi-Jun Yoo |
|
60
|
A
1.2Mpixels/s/mW 3-D Rendering Processor
For Portable Multimedia Application |
A-SSCC
2005 |
|
| Jeong-Ho
Woo, Min-Wuk Lee, Hyejung Kim, Ju-Ho
Sohn and Hoi-Jun Yoo |
|
59
|
Networks-on-chip
and Networks-in-Package for High-Performance
SoC Platforms |
A-SSCC
2005 |
 |
| Kangmin
Lee, Se-Joong Lee, Donghyun Kim, Kwanho
Kim, Gawon Kim, Joungho Kim, and Hoi-Jun
Yoo |
|
58
|
A
5.1-uW UHF RFID Tag Chip integrated
with Sensors for Wireless Environmental
Monitoring |
ESSCIRC
2005 |
 |
| Namjun
Cho, Seong-Jun Song, Jae-Youl Lee, Sunyoung
Kim, Shiho Kim, and Hoi-Jun Yoo |
|
57
|
A
Fixed-point Multimedia Co-processor
with 50Mvertices/s Programmable
SIMD Vertex Shader for Mobile Applications |
ESSCIRC
2005 |
|
| Ju-Ho
Sohn, Jeong-Ho Woo, Min-wuk Lee, Hye-Jung
Kim, Ramchan Woo, and Hoi-Jun Yoo |
|
56
|
An
Energy-Efficient Analog Front-End Circuit
for a Sub-1V Digital Hearing
Aid Chip |
SOVC
2005 |
|
| Sunyoung
Kim, Jae-Youl Lee, Seong-Jun Song, Namjun
Cho, and Hoi-Jun Yoo |
|
55
|
An
Autonomous SRAM with On-Chip Sensors
in an 80nm Double Stacked Cell
Technology |
SOVC
2005 |
|
| Kyomin
Sohn, Namjun Cho, Hyejung Kim, Kwanho
Kim, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun
Byun and Hoi-Jun Yoo |
|
54
|
Adaptive
Network-on-Chip with Wave-Front Train
Serialization Scheme |
SOVC
2005 |
|
| Se-Joong
Lee, Kwanho Kim, Hyejung Kim, Namjun
Cho, and Hoi-Jun Yoo |
|
53
|
A
Fixed-Point 3D Graphics Library with
Energy-Efficient Cache Architecture
for Mobile Multimedia Systems |
ISCAS
2005 |
|
| Min-wuk
Lee, Byeong-Gyu Nam, Ju-Ho Sohn, Namjun
Cho, Hyejung Kim, Kwanho Kim, and Hoi-Jun
Yoo |
|
52
|
A
8-uW, 0.3mm2 RF-Powered Transponder
With Temperature Sensor for Wireless
Environmental Monitoring |
ISCAS
2005 |
|
| Namjun
Cho, Seong-Jun Song, Jae-Youl Lee, Sunyoung
Kim, Shiho Kim, and Hoi-Jun Yoo |
|
51
|
A
0.9-V 67-uW Analog Front-End Using Adaptive-SNR
Technique for Digital Hearing
Aid |
ISCAS
2005 |
|
| Sunyoung
Kim, Jae-Youl Lee, Seong-Jun Song, Namjun
Cho, and Hoi-Jun Yoo |
|
50
|
An
Arbitration Look-Ahead Scheme for Reducing
End-to-End Latency in Networks-on-Chip |
ISCAS
2005 |
|
| Kwanho
Kim, Se-Joong Lee, Kangmin Lee and Hoi-Jun
Yoo |
|
49
|
A
Reconfigurable Crossbar Switch with
Adaptive Bandwidth Control for
Networks-on-Chip |
ISCAS
2005 |
|
| Donghyun
Kim, Kangmin Lee, Se-Joong Lee and Hoi-Jun
Yoo |
|
48
|
A
50Mvertices/s Graphics Processor with
Fixed-Point Programmable Vertex
Shader for Mobile Applications |
ISSCC
2005 |
|
| Ju-Ho
Sohn, Jeong-Ho Woo, Min-Wuk Lee, Hye-Jung
Kim, Ramchan Woo and Hoi-Jun Yoo |
|
47
|
SILENT
: Serialized Low Energy Transmission
Coding for On-Chip Interconnection
Networks |
ICCAD
2004 |
|
| Kangmin
Lee, Se-Joong Lee and Hoi-Jun Yoo |
|
46
|
Low
Energy Transmission Coding for On-Chip
Serial Communications |
ISOCC
2004
|
|
| Kangmin
Lee, Se-Joong Lee and Hoi-Jun Yoo |
|
45
|
A
Small Ripple Regulated Charge Pump with
Automatic Pumping Control Schemes |
ESSCIRC
2004 |
 |
| Sung-Eun
Kim, Seong-Jun Song, Jin Kyung Kim,
Sunyoung Kim, Jae-Youl Lee and Hoi-Jun
Yoo |
|
44
|
A
Programmable Vertex Shader with Fixed-Point
SIMD Datapath for Low Power Wireless
Applications |
Graphics
Hardware 2004 |
 |
| Ju-Ho
Sohn, Ramchan Woo and Hoi-Jun Yoo |
|
43
|
Arbitration
Latency Analysis of the Shared Channel
Architecture for High Performance
Multi-Master SoC |
AP-ASIC
2004 |
|
| Jisun
Suh and Hoi-Jun Yoo |
|
42
|
A
0.7fJ/bit/search, 2.2ns Search-time,
Hybrid type TCAM Architecture |
ISSCC
2004 |
 |
| Sungdae
Choi, Kyomin Sohn, Min-Wuk Lee, Sunyoung
Kim, Hye-Mi Choi, Donghyun Kim, Uk-Rae
Cho, Hyun-Geun Byun, Yun-Seung
Shin and Hoi-Jun Yoo |
|
41
|
A
51mW 1.6GHz On-Chip Network for Low-Power
Heterogeneous SoC Platform |
ISSCC
2004 |
|
| Kangmin
Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi
Choi, Donghyun Kim, Sunyoung Kim, Min-Wuk
Lee and Hoi-Jun Yoo |
|
40
|
A
Low-Power Graphics LSI integrating 29Mb
Embedded DRAM for Mobile Multimedia
Applications |
ASP-DAC
2004 |
 |
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, Young-Don Bae and Hoi-Jun Yoo |
|
39
|
An
analysis and implementation of high
fairness arbitration mechanism by
using level-table and static priority
orders in shared bus architecture |
IP
SoC 2003 |
|
| Jisuhn
Suh and Hoi-Jun Yoo |
|
38
|
A
Distributed On-Chip Crossbar Switch
Scheduler for On-Chip Network |
CICC
2003 |
|
| Kangmin
Lee, Se-Joong Lee and Hoi-Jun Yoo |
|
37
|
A
10Gbps/port 8x8 Shared Bus Switch with
embedded DRAM Hierarchical Output
Buffer |
ESSCIRC
2003 |
|
| Kangmin
Lee, Se-Joong Lee and Hoi-Jun Yoo |
|
36
|
A
High-Speed and Lightweight On-Chip Crossbar
Switch Scheduler for On-Chip
Interconnection Networks |
ESSCIRC
2003 |
|
| Kangmin
Lee, Se-Joong Lee and Hoi-Jun Yoo |
|
35
|
A
Low-Power 3D Rendering Engine with Two
Texture Units and 29Mb Embedded
DRAM for 3G Multimedia Terminals |
ESSCIRC
2003 |
|
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, and Hoi-Jun Yoo |
|
34
|
A
Low-Power and High-Performance 2D/3D
Graphics Accelerator for Mobile
Multimedia Applications |
HotChips
2003 |
 |
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, Young-Don Bae and Hoi-Jun Yoo |
|
33
|
CMOS
Optical Receiver Chipset for Gigabit
Ethernet Applications |
ISCAS
2003 |
 |
| Sung-Eun
Kim, Seong-Jun Song, Sung-Min Park and
Hoi-Jun Yoo |
|
32
|
An
800MHz Star-Connected On-Chip Network
for Application to Systems on
a Chip |
ISSCC
2003 |
|
| Se-Joong
Lee, Seong-Jun Song, Kangmin Lee, Jeong-Ho
Woo, Sung-Eun Kim, Byeong-Gyu Nam and
Hoi-Jun Yoo |
|
31
|
A
210mW Graphics LSI Implementing Full
3D Pipeline with 264Mtexels/s
Texturing for Mobile Multimedia Applications |
ISSCC
2003 |
|
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, Young-Don Bae, Chi-Weon Yoon,
Byeong- Gyu Nam,
Jeong-Ho Woo, Sung-Eun Kim, In-Cheol
Park, Sungwon Shin, Kyung-Dong Yoo,
Jin-Yong Chung and Hoi-Jun Yoo |
|
30
|
A
practical method to use eDRAM in the
shared bus packet switch |
GLOBECOM
2002 |
 |
| Kangmin
Lee, Se-joong Lee and Hoi-Jun Yoo |
|
29
|
Design
and Implementation of Read-Compare-Write
circuits for low power Multi-Gigabit
DRAM |
SSDM
2002 |
 |
| Sungdae
Choi, Yong-Ha Park and Hoi-Jun Yoo |
|
28
|
Optimization
of portable system architecture for
real time 3D graphics |
ISCAS
2002 |
 |
| Ju-ho
Sohn, Ramchan Woo and Hoi-Jun Yoo |
|
27
|
Gigabit
Throughput CMOS ICs for Optical Interconnection
Applications |
SSDM
2002 |
 |
| Hoi-Jun
Yoo |
|
26
|
A
4-Gb/s Clock and Data Recovery Circuit
Using Four-Phase 1/8-Rate Clock |
ESSCIRC
2002 |
|
| Seong-Jun
Song, Jaeseo Lee, Sung-Min Park and
Hoi-Jun Yoo |
|
25
|
Low
Power MPEG-4 Video Codec Hardware for
Portable Applications |
CoolChips
2002 |
 |
| Chi-Weon
Yoon and Hoi-Jun Yoo |
|
24
|
A
Multichip-on-Oxide 1.0Gb/s 80dB¥Ø Fully-Differential
CMOS Transimpedance Amplifier
for Optical Interconnect Applications |
ISSCC
2002 |
|
| Jaeseo
Lee, Seong-Jun Song, Sung Min Park,
Choong-Mo Nam, Young-Se Kwon and Hoi-Jun Yoo |
|
23
|
Embedded
DRAM (eDRAM) Power-Energy Estimation
for System-on-a-Chip (SoC) Applications |
ASP-DAC
2002 |
 |
| Yong-Ha
Park, Jeonghoon Kook and Hoi-Jun Yoo |
|
22
|
SOC
Design Approaches Optimized for VLSI
Fabrication Technologies |
SCI
2001 ISAS 2001 |
¡¡
|
| Se-Jeong
Park, Chi-Weon Yoon and Hoi-Jun Yoo |
|
21
|
120mW
Embedded 3D Graphics Rendering Engine
with 64Mb Logically Local Frame
Buffer and 3.2GByte/s Run-time Reconfigurable
Bus for PDA-Chip |
SOVC
2001 |
|
| Ramchan
Woo, Chi-Weon Yoon, Jeonghoon Kook,
Se-Joong Lee, Kangmin Lee, Yong-Ha Park
and Hoi-Jun Yoo |
|
20
|
Low
Power Motion Compensation Block IP with
embedded DRAM Macro for Portable
Multimedia Applications |
SOVC
2001 |
|
| Chi-Weon
Yoon, Jeonghoon Kook, Ramchan Woo, Se-Joong
Lee, Kangmin Lee and Hoi-Jun Yoo |
|
19
|
480ps
64-bit Race Logic Adder |
SOVC
2001 |
|
| Se-Joong
Lee, Ramchan Woo and Hoi-Jun Yoo |
|
18
|
A
Reconfigurable Multilevel Parallel Graphics
Cache Memory with75 GB/s Parallel
Cache Replacement Bandwidth |
SOVC
2001 |
 |
| Se-Jeong
Park, Jeong-Su Kim, Ramchan Woo, Se-Joong
Lee, Kang-Min Lee, Tae-Hum Yang,
Jin-Yong Jung and Hoi-Jun Yoo |
|
17
|
Single
Chip 3D Rendering Engine Integrating
Embedded DRAM Frame Buffer and
Hierarchical Octet Tree (HOT) Array
Processor with Bandwidth Amplification |
ASP-DAC
2001 |
 |
| Yong-Ha
Park, Sun-Ho Han and Hoi-Jun Yoo (The
outstanding Design Award) |
|
16
|
80/20MHz
160mW Multimedia Processor integrated
with Embedded DRAM MPEG-4 Accelerator
3D Rendering Engine for Mobile
Applications |
ISSCC
2001 |
|
| Chi-Weon
Yoon, Ramchan Woo, Jeonghoon Kook, Se-Joong
Lee, Kangmin Lee, Young-Don Bae,
In-Cheol Park and Hoi-Jun Yoo |
|
15
|
A
Comparative Analysis of a DDR-SDRAM,
a D-RDRAM and a DDR- FCRAM Using
a POPeye Simulator |
ISCAS
2001 |
|
| Kangmin
Lee, Chi-Weon Yoon, Ramchan Woo, Jeonghoon
Kook and Hoi-Jun Yoo |
|
14
|
Design
and Implementation of CMOS LVDS 2.5Gb/s
Transmitter and 1.3Gb/s Receiver
for Optical Interconnections |
ISCAS
2001 |
 |
| Jaeseo
Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik
Song, Wang-Joo Lee and Hoi-Jun Yoo |
|
13
|
A
7.1GB/s Low Power 3D Rendering Engine
in 2D Array Embedded Memory Logic
CMOS |
ISSCC
2000 |
 |
| Yong-Ha
Park, Sun-Ho Han, Jung-Su Kim, Se-Joong
Lee, Jeong-Hun Kook, Jae-Won Lim, Ramchan
Woo, Hoi-Jun Yoo, Jeong-Hwan
Lee and Jay-Hun Lee |
|
12
|
A
Novel High Speed Low Power Logic Family
: Race Logic |
ESSCIRC
2000 |
|
| Se-Joong
Lee and Hoi-Jun Yoo |
|
11
|
A
Single Bit line Writng Scheme for Low
Power Reconfigurable I/O DRAM
Macro |
ESSCIRC
2000 |
 |
| Jeonghon
Kook and Hoi-Jun Yoo |
|
10
|
One
chip - low power Digital-TCXO with Sub-ppm
Accuracy |
ISCAS
2000 |
|
| Se-Joong
Lee, Jin-Ho Han, Seung-Ho Hank, Joe-Ho
Lee, Jung-Su Kim, Min-Kyu Je and Hoi-Jun
Yoo |
|
9
|
A
670ps, 64bit Dynamic Low-Power Adder
Design |
ISCAS
2000 |
|
| Ramchan
Woo, Se-Joong Lee and Hoi-Jun Yoo |
|
8
|
POPeye:
A System Analysis Tool for DRAM Performance
Measurement |
ICVC
2000 |
 |
| Yon-Kyun
Im, Chi-Weon Yoon, Hoi-Jun Yoo and Tae-Sung
Jung |
|
7
|
A
330MHz Low Jitter Fast Locking Direct
Skew Compensation DLL |
ISSCC
2000 |
 |
| Joo-Ho
Lee, Seon-Ho Han and Hoi-Jun Yoo |
|
6
|
A
VPM(Virtual Pipelined Memory) Architecture
for a Fast Row-Cycle DRAM |
APASIC
1999 |
 |
| Chi-Weon
Yoon, Yon-Kyun Im, Seon-Ho Han, Hoi-Jun
Yoo and Tae-Sung Jung |
|
5
|
7.1GB/s
Bandwidth 3D Rendering Engine Using
the EML Technology |
ICVC
1999 |
 |
| Yong-Ha
Park, Ramchan Woo, Seon-Ho Han, Jung-Su
Kim, Se-Joong Lee, Jeong-Hoon Kook,
Jae-Won Lim and Hoi-Jun Yoo |
|
4
|
Fast
Lock-On Time Mixed Mode DLL With 10ps
Jitter |
ISSCC
1999 |
 |
| Seon-Ho
Han, Joo-Ho Lee and Hoi-Jun Yoo |
|
3
|
A
Fast Lock-On Time Mixed Mode DLL With
10ps Jitter |
APASIC
1999 |
 |
| Seon-Ho
Han, Joo-Ho Lee and Hoi-Jun Yoo |
|
2
|
The
CMOS Temperature Sensor and Cyclic ADC
For Low Power Single Chip DTCXO |
ICVC
1999 |
 |
| Joo-Ho
Lee, Seon-Ho Han and Hoi-Jun Yoo |
|
1
|
A
Fast Synchronous Pipelined DRAM (SP-DRAM)
Architecture with SRAM Buffers |
ICVC
1999 |
|
| Chi-Weon
Yoon, Yon-Kyun Im, Seon-Ho Han, Hoi-Jun
Yoo and Tae-Sung Jung |