Home > Publication > International Patent

No.

Title

No.

Date

Status

Inventors

20

Apparatus and Method for Compensating for Inductance in Inductive Coupling Communications

U.S. Patent
No. 8,244,187

 

  Jerald Yoo and Hoi-Jun Yoo

19

Fabric Type Semiconductor Device Package And Methods Of Installing And Manufacturing The Same

U.S. Patent
No. 7,638,885

 

  Yongsang Kim, Hyejeong Kim and Hoi-Jun Yoo

18

Wearable Monitoring Apparatus And Driving Method Thereof

U.S. Patent
No. 8,428,683

Apr 23, 2013

 

  Jerald Yoo and Hoi-Jun Yoo

17

Digital Hearing Aid Adaptive to structures of human external ear canals

U.S. Patent
No. 8,150,049

Apr 03, 2012

 

  Sunyoung Kim, Jerald Yoo and Hoi-Jun Yoo

16

Apparatus for Receiving Wide Band Pulse Signal in Communication Channel Using Human Body

U.S. Patent
No. 7,650,113

Jan 19, 2010

 

  Seong-Jun Song and Hoi-Jun Yoo

15

Temperature-Adaptive Capacitor Block and Temperature-Compensated
Crystal Oscillator using it

Japanese Application
No. 2000-134740

Nov 16, 2006

U.S. Patent
No. 6281761

D.E. Patent
No. 100 23 350

   Hyungchul Sin, Minkyu Jae, Seungho Han and Hoi-Jun Yoo

14

Pipeline Structure of Memory for High-Fast Row-Cycle

Japanese Application
No. 2001-520413

Jun 30, 2006

U.S. Patent
No. 6545936

   Ramchan Woo and Hoi-Jun Yoo

13

 Division Unit of 3D Computer Graphics Systems.

Japanese Application
No. 2004-167983

Jan 3, 2006

U.S. Patent
No. 6545936

   Ramchan Woo and Hoi-Jun Yoo

12

 Low Power Memory Storing Method for Compressed MPEG Image
and Its Frame Buffer Structure

U.S. Patent
No. 6,907,978

Jun 14, 2005

 

  Chi-Weon Yoon and Hoi-Jun Yoo

11

Cache Memory for Texture Mapping Process in Three-Dimensional Graphics and Method for Reducing Penalty due to Cache Miss

U.S. Patent
No. 6,891,546

May 10, 2005

 

  Se-Jeong Park and Hoi-Jun Yoo

10

 The Efficient Management of Memory Cell Array

U.S. Patent
No. 6,608,793

Aug 19, 2003

 

  Yong-Ha Park and Hoi-Jun Yoo

9

 Division Unit of 3D Computer Graphics Systems.

Japanese Application
No. 2003-37038

Jun 10, 2003

U.S. Patent
No. 6545936

   Ramchan Woo and Hoi-Jun Yoo

8

 The Race Logic Circuit

U.S. Patent
No. 6,661,256

Dec 9, 2003

 

   Se-Joong Lee and Hoi-Jun Yoo

7

 Method for Storing Data to Memory Cell

U.S. Patent
No. 6,327,204

Dec 4, 2003

 

   Jeonghoon Kook and Hoi-Jun Yoo

6

 Pipeline Structure of Memory for High-Fast Row-Cycle

Japanese Application
No.2001-520413

Apr 23, 2001

U.S. Patent
No. 6545936

Apr 8, 2003

   Chi-Weon Yoon and Hoi-Jun Yoo

5

 Low Power Memory Storing Method for Compressed  MPEG Image and Its Frame Buffer Structure

U.S. Application
No. 10/055,916

Jan 28, 2002

   Chi-weon Yoon and Hoi-Jun Yoo

4

 Method for Memory Addressing

U.S. Patent
No. 6400640

Apr 4, 2002

 

   Ramchan Woo, Chi-Weon Yoon and Hoi-Jun Yoo

3

 The Efficient Management of Memory Cell Array

U.S. Application
No. 09/765,652

Jan 22, 2001

   Yong-Ha Park and Hoi-Jun Yoo

2

 A Low Power Instruction Decoding Method for Microprocessor

Taiwan Application
No. 89,123,526

Nov 8, 2000

   Ramchan Woo and Hoi-Jun Yoo

1

 Cache Memory for Texture Mapping Process in Three-Dimensional Graphics and Method for Reducing Penalty Due to Cache Miss

U.S. Patent
No. 6,891,546

May 10, 2005

   Se-Jeong Park, Kyu-Ho Park and Hoi-Jun Yoo

#1233, School of Electrical Engineering, KAIST, 291 Daehak-ro (373-1 Guseong-dong), Yuseong-gu,
Daejeon 34141, Republic of Korea / Tel. +82-42-350-8068 / Fax. +82-42-350-3410 / Mail: sslmaster@kaist.ac.kr
Copyright (C) 2017, SEMICONDUCTOR SYSTEM LAB., All Rights Reserved.