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No.

Cover

Title

Authors

Publisher

Date

7

Embedded
Memories for
Nano-Scale
VLSIs

*Ch. 2. Embedded Memory Architecture for Low-Power Application is written by Hoi-Jun Yoo

Springer

2009

Nano-Scale
VLSI¸¦ À§ÇÑ
ÀÓº£µðµå
¸Þ¸ð¸®

*Ch. 2. Embedded Memory Architecture for Low-Power Application ºÎºÐ À¯È¸ÁØ ÁöÀ½

Springer

6

Circuits
at the
Nanoscale

*Ch. 28. Unified Computer Arithmetic for Handleheld GPUs is written by Hoi-Jun Yoo

CRC Press

2009

Nanoscale
ÀüÀÚȸ·Î

*Ch. 28. Unified Computer Arithmetic for Handleheld GPUs ºÎºÐ À¯È¸ÁØ ÁöÀ½

CRC ÇÁ·¹½º

5

Low-Power NoC
for
High-Performance
SoC Design

Hoi-Jun Yoo, Kangmin Lee,
Jun Kyoung Kim

CRC Press

2008

°í¼º´É SoC µðÀÚÀÎÀ»
À§ÇÑ
ÀúÀü·Â NoC

À¯È¸ÁØ, À̰­¹Î, ±èÁذæ ÁöÀ½

CRC ÇÁ·¹½º

4

Networks on Chips : Technology and Tools

*Ch. 3. Physical Network Layer a and
Ch. 9. Designs and Implementations of NoC-Based SoCs are written by Hoi-Jun Yoo

Morgan Kaufmann

2006

³×Æ®¿öÅ© ¿Â Ĩ : Technology and Tools

*Ch. 3. Physical Network Layer ¿Í
Ch. 9. Designs and Implementations of NoC-Based SoCs ºÎºÐ À¯È¸ÁØ ÁöÀ½

¸ð°Ç Ä«¿ìÇÁ¸¸

3

Future Memory : FRAM

Hoi-Jun Yoo,
S-H Kim, J-S Yoo

Sigma Press

2000

¹Ì·¡ÀÇ ¸Þ¸ð¸® : FRAM

À¯È¸ÁØ, ±è½ÃÈ£, À¯Á¾¼± ¿Å±è

½Ã±×¸¶ ÇÁ·¹½º

2

High-performance DRAM

Hoi-Jun Yoo

KAIST IDEC

1998

°í¼º´É DRAM

À¯È¸ÁØ

KAIST IDEC ÃâÆÇºÎ, ½Ã±×¸¶ ÇÁ·¹½º

1

DRAM Design

Hoi-Jun Yoo

KAIST IDEC

1997

DRAMÀÇ ¼³°è

À¯È¸ÁØ

KAIST IDEC ÃâÆÇºÎ, È«¸ª°úÇÐ ÃâÆÇ»ç