|
No. |
Title |
Publication |
Down
|
| Authors |
2010 |
|
61
|
Familiarity based unified visual attention model for fast and robust object
recognition |
PR 2010
|
|
| Seungjin Lee, Kwanho Kim, Joo-Young Kim, Minsu Kim, and Hoi-Jun Yoo |
|
60
|
ECG Signal Compression and Classification Algorithm With Quad Level Vector for ECG Holter System |
TITB 2010
|
|
| Hyejung Kim, Refet Firat Yazicioglu, Patrick Merken, Chris Van Hoof, and Hoi-Jun Yoo |
|
59
|
A 5.2mW Self-Configured Wearable Body Sensor Network Controller and a 12¥ìW 54.9% Efficiency Wirelessly Powered Sensor for Continuous Health Monitoring System
|
JSSC 2010
|
|
| Jerald Yoo, Long Yan, Seulki Lee , Yongsang Kim, Hyejung Kim, Binhee Kim, and Hoi-Jun Yoo |
|
58
|
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine |
JSSC 2010
|
|
| Joo-Young Kim, Minsu Kim, Seungjin Lee , Jinwook Oh, Kwanho Kim, and Hoi-Jun Yoo |
2009 |
|
57
|
A 10.8 mW Body Channel Communication/MICS Dual-Band Transceiver for a Unified Body Sensor Network Controller |
JSSC 2009
|
|
| Namjun Cho, Joonsung Bae, and Hoi-Jun Yoo |
|
56
|
A Configurable Heterogeneous Multicore Architecture with Cellular Neural Network for Real-Time Object Recognition |
TCSVT 2009
|
|
| Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, and Hoi-Jun Yoo |
|
55
|
Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining |
MICRO 2009
|
|
| Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Sejong Oh, and Hoi-Jun Yoo |
|
54
|
A 1.12 pJ/b Inductive Transceiver With a Fault-Tolerant Network Switch for Multi-Layer Wearable Body Area Network Applications |
JSSC 2009
|
|
| Jerald Yoo, Seulki Lee, and Hoi-Jun Yoo |
|
53
|
A Wearable ECG Acquisition System With Compact Planar-Fashionable Circuit Board-Based Shirt |
TITB 2009
|
|
| Jerald Yoo, Long Yan, Seulki Lee, Hyejung Kim, and Hoi-Jun Yoo |
|
52
|
Planar Fashionable Circuit Board Technology and Its Applications |
JSTS 2009
|
|
| Seulki Lee, Binhee Kim, and Hoi-Jun Yoo |
|
51
|
A Planar MICS Band Antenna Combined With a Body Channel Communication Electrode for Body Sensor Network |
TMTT 2009
|
|
| Namjun Cho, Taehwan Roh, Joonsung Bae, and Hoi-Jun Yoo |
|
50
|
A 152-mW Mobile Multimedia SoC With
Fully Programmable 3-D Graphics and
MPEG4/H.264/JPEG |
TVLSI 2009
|
|
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, and Hoi-Jun Yoo |
|
49
|
A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices |
CG&A 2009
|
|
| Jeong-Ho Woo, Hyejung Kim, and Hoi-Jun Yoo |
|
48
|
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor |
IET CDT 2009
|
|
| Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Se-Joong Lee, and Hoi-Jun Yoo |
|
47
|
81.6 GOPS Object Recognition Processor Based on
a Memory-Centric NoC |
TVLSI 2009
|
|
| Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Se-Joong Lee, and Hoi-Jun Yoo |
|
46
|
A 200-Mbps 0.02-nJ/b Dual-Mode Inductive Coupling Transceiver for cm-Range Multimedia Application |
TCAS 2009
|
|
| Seulki Lee, Jerald Yoo, and Hoi-Jun Yoo |
|
45
|
A 60 kb/s-10 Mb/s Adaptive Frequency Hopping
Transceiver for Interference-Resilient Body Channel
Communication |
JSSC 2009
|
|
| Namjun Cho, Long Yan, Joonsung Bae, and Hoi-Jun Yoo |
|
44
|
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine |
JSSC 2009
|
|
| Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, and Hoi-Jun Yoo |
2007 ~ 2008 |
|
43
|
A 195 mW, 9.1 MVerices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices |
JSSC 2008
|
|
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, and Hoi-Jun Yoo |
|
42
|
A 195 mW/152 mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG |
JSSC 2008
|
|
| Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, and Hoi-Jun Yoo |
|
41
|
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems |
TOC 2008
|
|
| Byeong-Gyu Nam, Hyejung Kim, and Hoi-Jun Yoo |
|
40
|
A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations
|
JSSC 2008
|
|
| Sunyoung Kim, Seung Jin Lee, Namjun Cho, Seong-Jun Song, and Hoi-Jun Yoo |
|
39
|
A 0.9 V 96uW Fully Operational Digital Hearing Aid Chip |
JSSC 2007
|
|
| Sunyoung Kim, Namjun Cho, Seong-Jun Song, and Hoi-Jun Yoo |
|
38
|
A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications |
JSSC 2007
|
|
| Seong-Jun Song, Namjun Cho, and Hoi-Jun Yoo |
|
37
|
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems |
JSSC 2007
|
|
| Byeong-Gyu Nam, Hyejung Kim, and Hoi-Jun Yoo |
|
36
|
The Human Body Characteristics as a Signal Transmission Medium for Intrabody Communication |
TMTT 2007 |
 |
| Namjun Cho, Jerald Yoo, Seong-Jun Song, Jeabin Lee, Seonghyun Jeon, and Hoi-Jun Yoo |
2006 |
|
35
|
A
231-MHz, 2.18-mW 32-bit Logarithmic
Arithmetic Unit for Fixed-Point 3-D
Graphics System |
JSSC 2006 |
 |
| Hyejung
Kim, Byeong-Gyu Nam, Ju-Ho Sohn, Jeong-Ho
Woo, and Hoi-Jun Yoo |
|
34
|
A
155-mW 50-Mvertices/s Graphics Processor
With Fixed-Point
Programmable Vertex Shader
for Mobile Applications |
JSSC 2006 |
 |
| Ju-Ho
Sohn, Jeong-Ho Woo, Min-Wuk Lee, Hye-Jung
Kim, Ramchan Woo, and Hoi-Jun Yoo |
|
33
|
An
Energy-Efficient Analog Front-End Circuit
for a Sub-1-V Digital Hearing
Aid Chip |
JSSC 2006 |
 |
| Sunyoung
Kim, Jae-Youl Lee, Seong-Jun Song, Namjun
Cho, and Hoi-Jun Yoo |
|
32
|
An
Autonomous SRAM With On-Chip Sensors
in an 80-nm Double Stacked
Cell Technology |
JSSC 2006 |
 |
| Kyomin
Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun
Byun, and Hoi-Jun Yoo |
|
31
|
Low-Power
Network-on-Chip for High-Performance
SoC Design |
TVLSI 2006 |
 |
| Kangmin
Lee, Se-Joong Lee, and Hoi-Jun Yoo |
|
30
|
A
Regulated Charge Pump With Small Ripple
Voltage and Fast Start-Up |
JSSC 2006 |
 |
| Jae-Youl
Lee, Sung-Eun Kim, Seong-Jun Song, Jin-Kyung
Kim, Sunyoung Kim, and Hoi-Jun Yoo |
2004 ~ 2005 |
|
29
|
Low
Power 3D Graphics Processors for Mobile
Terminals |
CM 2005 |
 |
| Ju-Ho
Sohn, Yong-Ha Park, Chi-Weon Yoon, Ramchan
Woo, Se-Jeong Park, and Hoi-Jun Yoo |
|
28
|
Development
of a 3-D Graphics Rendering Engine with
Lighting Acceleration
for Handheld Multimedia
Systems |
CE 2005 |
 |
| Byeong-Gyu
Nam, Min-Wuk Lee, and Hoi-Jun Yoo |
|
27
|
Analysis
and Implementation of Practical Cost-Effective
Network-on-Chips |
DTC 2005 |
 |
| Se-Joong
Lee, Kangmin Lee, and Hoi-Jun Yoo |
|
26
|
Packet-Switched
On-Chip Interconnection Network for
System-on-Chip
Applications |
TCAS 2005 |
 |
| Se-Joong
Lee, Kangmin Lee, Seong-Jun Song, and
Hoi-Jun Yoo |
|
25
|
A
0.7-fJ/Bit/Search 2.2-ns Search Time
Hybrid-Type TCAM Architecture |
JSSC 2005 |
 |
| Sungdae
Choi, Kyomin Sohn, and Hoi-Jun Yoo |
|
24
|
A
Low-Power 3-D Rendering Engine With
Two Texture Units and 29-Mb
Embedded DRAM for 3G Multimedia
Terminals |
JSSC 2004 |
 |
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, Young-Don Bae, and Hoi-Jun Yoo |
|
23
|
1-Gb/s
80-dB¥Ø Fully Differential CMOS Transimpedance
Amplifier in Multichip
on Oxide Technology for
Optical Interconnects |
JSSC 2004 |
 |
| Sung
Min Park, Jaeseo Lee, and Hoi-Jun Yoo |
|
22
|
A
210-mW Graphics LSI Implementing Full
3-D Pipeline With 264 Mtexels/s
Texturing for Movile Multimedia
Applications |
JSSC 2004 |
 |
| Ramchan
Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun
Song, and Hoi-Jun Yoo |
|
21
|
A1.25-Gb/s
Regulated Cascode CMOS Transimpedance
Amplifier for Gigabit
Ethernet Applications |
JSSC 2004 |
 |
| Sung
Min Park and Hoi-Jun Yoo |
2001 ~ 2003 |
|
20
|
A
4Gb/s CMOS Clock and Data Recovery Circuit
Using 1/8-Rate Clock
Technique |
JSSC 2003 |
 |
| Seong-Jun
Song, Sung Min Park and Hoi-Jun Yoo |
|
19
|
Low
Power Motion Estimation and Motion Compensation
Block IPs in MPEG-4
Video Codec Hardware for
Portable Applications |
IEICE 2003 |
 |
| Chi-Weon
Yoon and Hoi-Jun Yoo |
|
18
|
2.5
Gbps CMOS transimpedance amplifier for
optical communication
applications |
EL 2003 |
 |
| Sung
Min Park and Hoi-Jun Yoo |
|
17
|
A
120-mW 3D rendering engine with 6-Mb
embedded DRAM and 3.2GB/s
runtime reconfigurable
bus for PDA chip |
JSSC 2002 |
 |
| Ramchan
Woo, Chi-Weon Yoon, Jeonghoon Koo, Se-Joong
Lee and Hoi-Jun Yoo |
|
16
|
A
Reconfigurable Multilevel Parallel Texture
Cache Memory With 75-GB/s
Parallel Cache Replacement
Bandwidth |
JSSC 2002 |
 |
| Se-Jeong
Park, Jeong-Su Kim, Ramchan Woo, Se-Joong
Lee, Kangmin Lee, Tae-Hum Yang, Jin-Yong
Jung
and Hoi-Jun Yoo |
|
15
|
Embedded
DRAM (eDRAM) Power Energy Estimation
Using Signal
Swing-Based Analytical
Model |
IEICE 2002 |
 |
| Yong-Ha
Park |
|
14
|
A
Bit-Wise Read-Compare-Write Scheme for
Low Power Read-Modify-Write
Scheme |
EL 2002 |
 |
| Yong-Ha
Park, Sungdae Choi and Hoi-Jun Yoo |
|
13
|
Race
Logic Architecture (RALA): A Novel Logic
Concept Using the Race
Scheme of Input Variables |
JSSC 2002 |
 |
| Se-Joong
Lee and Hoi-Jun Yoo |
|
12
|
An
80/20-MHz 160-mW Multimedia Processor
Integrated with Embedded
DRAM, MPEG-4 Accelerator,
and 3-D Rendering Engine for Mobile
Applications |
JSSC 2001 |
 |
| Chi-Weon
Yoon, Ramchan Woo, Jeonghoon Kook, Se-Joong
Lee, Kangmin Lee and Hoi-Jun Yoo |
|
11
|
Hidden
Double Data Transfer Scheme for MDL
Design |
EL 2001 |
 |
| Se-Jeong
Park and Hoi-Jun Yoo |
|
10
|
A
7.1GB/s Low Power 3D Rendering Engine
in 2D Array Embedded Memory Logic CMOS
for Portable Multimedia System |
JSSC 2001 |
 |
| Yong-Ha
Park, Seon-Ho Han, Jeong-Hwan Lee and
Hoi-Jun Yoo |
|
9
|
POPeye:
A Simulator for a DRAM Performance Evaluation |
JSTS 2001 |
 |
| Kangmin
Lee, Chi-Weon Yoon, Ramchan Woo, Jeonghoon
Kook and Hoi-Jun Yoo |
1996 ~ 1999 |
|
8
|
Fast
Lock-On Time Mixed Mode DLL With 10ps
Jitter |
EL 1999 |
 |
| Seon-Ho
Han, Joo-Ho Lee and Hoi-Jun Yoo |
|
7
|
Boosted
Charge Transfer Preamplifier For Low
Power Gb-Scale GRAM
Electron |
EL 1998 |
 |
| Jong-Shik
Kim, Hoi-jun Yoo and Kwang-seok Seo |
|
6
|
Dual
VT Self-timed CMOS Logic for Low Subthreshold
Current
Multi-gigabit Synchronous
DRAM |
TCAS 1998 |
 |
| Hoi-Jun
Yoo |
|
5
|
A
Low Noise Folded Bit-Line Sensing Architecture
for Multi-Gb
DRAM with Ultra High Density
6F2 Cell |
JSSC 1998 |
 |
| Jong-Shik
Kim, Yu-soo Choi, Hoi-Jun Yoo and Kwang-seok
Seo |
|
4
|
A
Study of Pipeline Architectures for
High Speed Synchronous DRAM |
JSSC 1997 |
 |
| Hoi-Jun
Yoo |
|
3
|
A
Low Voltage High Speed Self-Timed CMOS
Logic for the Multi-giga bit
Synchronous DRAM Application |
IEICE 1997 |
 |
| Hoi-Jun
Yoo |
|
2
|
An
Analytical Model for the Effect of Graded
Gate Oxide on the Channel
Electric Field in MOSFET's
with Lightly Doped Drain Structure |
SSE 1997 |
¡¡
|
| J.S.Kim,
Hoi-Jun Yoo and K.S. Seo |
|
1
|
High
Speed Latchup Resistant CMOS Data Output
Buffer for Sub-micron
DRAM Application |
EL 1996 |
 |
| Hoi-Jun
Yoo |