In the era of System-on-Chip,
the communication architecture that
interconnects
distinct IPs plays very important role.
On-Chip Network is the one of communication architectures, that is promissing
because it has good scalability, provides
high bandwidth and predictable latency,
and shows various interesting features.
Our study focuses on optimal topology,
switch structure, flow control, high-speed
and low power interconnection, and the
implementation of all of these.
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