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Wang-Joo Lee Sungmin Park Se-Jeong Park Jae-Youl Lee Jun-Kyoung Kim
Sungdae Choi Sejong Oh Jeong-Ho Woo Jerald Yoo Joo-Young Kim
Seungjin Lee Joonsung Bae Jinwook Oh Taehwan Roh Junyoung Park
Kiseok Song Gyeonghoon Kim Injoon Hong Unsoo Ha Youchang Kim
Kyuho Lee Dongjoo Shin
Se-Jeong Park Yong-Ha Park Chi-Weon Yoon Ramchan Woo Se-Joong Lee
Kangmin Lee Sungdae Choi Ju-Ho Sohn Byeong-Gyu Nam Kyomin Sohn
Seong-Jun Song Jeong-Ho Woo Sunyoung Kim Donghyun Kim Namjun Cho
Kwanho Kim Hyejung Kim Jerald Yoo Joo-Young Kim Seungjin Lee
Long Yan Seulki Lee Joonsung Bae Jinwook Oh Taehwan Roh
Junyoung Park Kiseok Song Hyungwoo Lee Gyeonghoon Kim Sunjoo Hong
Hyunwoo Cho Injoon Hong Unsoo Ha Youchang Kim Kyuho Lee
Seongwook Park Kyeongryeol Bong Dongjoo Shin
Joo-Ho Lee Jae-Won Lim Jinho Han Jeonghoon Kook Jaeseo Lee
Sung-Eun Kim Jin Kyung Kim Min-Wuk Lee Jeabin Lee Yongsang Kim
Minsu Kim Binhee Kim Joonsoo Kwon Hyunki Kim Jiwoon Lee



Se-Joong Lee (À̼¼Áß)

   Ph.D.

¤ıResearch Interest
-  On-Chip Network for System-On-Chip Design
    (This includes the study of optimal topology, switch structure, flow control, high-speed interconnection,
     and the implementation of all of these.)
-  High-speed Digital Logic Design
    (This includes the study of the fundamental concepts of logic operations and circuit level contributions
     for various logic schemes)
¤ıContact Information
Qualcomm,
5580 Morehouse Drive,
San Diego, CA 92121, USA
Email: sejoongl@qti.qualcomm.com
¤ıEducation
2005. 8     Ph.D. in EE, Korea Advanced Institute of Science and Technology
                 Thesis: Cost-Optimization and Chip Implemenation of On-Chip Network
2001. 2     M.S. in EE, Korea Advanced Institute of Science and Technology
                 Thesis: Performance Analysis of Gigabit Ethernet Shared-Memory Switch with Embedded DRAM
1999. 2     B.S. in EE, Korea Advanced Institute of Science and Technology
1995. 2     Daejeon Science High School
¤ıWork Experience
2012. 6 ~           Qualcomm, San Diego
2005. 12 ~ 2012. 6   Texas Instruments, Dallas
¤ıPublications
- International Journal Papers
Analysis and Implementation of Practical Cost-Effective Network-on-Chips
Se-Joong Lee, Kangmin Lee and Hoi-Jun Yoo
IEEE Design & Test of Computers (Special Issue for NoC), Sep.-Oct. 2005
Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications
Se-Joong Lee, Kangmin Lee, Seong-Jun Song and Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems II (TCAS), vol. 52, No. 6, pp. 308-312, June 2005
Race Logic Architecture (RALA): A Novel Logic Concept Using the Race Scheme of Input Variables
Se-Joong Lee and Hoi-Jun Yoo
IEEE Journal of Solid-State Circuit (JSSC), Vol. 37, No. 2, pp. 191-201, Feb. 2002
- International Conference Papers
A Network-on-Chip with 3Gbps/wire Serialized On-chip Interconnect Using Adaptive Control Schemes
Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho and Hoi-Jun Yoo
Design, Automation and Test in Europe (DATE), Mar. 2006
Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme
Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho and Hoi-Jun Yoo
IEEE Symposium on VLSI (SOVC), May 2005
An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip
Se-Joong Lee, Seong-Jun Song, Kangmin Lee, Jeong-Ho Woo, Sung-Eun Kim, Byeong-Gyu and Hoi-Jun Yoo
IEEE International Solid-State Circuits Conference (ISSCC), pp.468 - 469, 2003
480ps 64-bit Race Logic Adder
Se-Joong Lee, Ramchan Woo and Hoi-Jun Yoo
IEEE Symposium on VLSI Circuits (SOVC), pp. 99-102, 2001
A Novel High Speed Low Power Logic Family : Race Logic
Se-Joong Lee and Hoi-Jun Yoo
IEEE European Solid-State Circuit Conference (ESSCIRC), pp. 420-423, Sept. 2000
One chip - low power Digital-TCXO with Sub-ppm Accuracy
Se-Joong Lee and Hoi-Jun Yoo
IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 17-20, May 28, 2000

#1233, School of Electrical Engineering, KAIST, 291 Daehak-ro (373-1 Guseong-dong), Yuseong-gu,
Daejeon 34141, Republic of Korea / Tel. +82-42-350-8068 / Fax. +82-42-350-3410 / Mail: sslmaster@kaist.ac.kr
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