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Se-Joong Lee (이세중)
Ph.D. |
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| ㆍResearch
Interest |
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- On-Chip Network for
System-On-Chip Design
(This
includes the study of optimal
topology, switch structure, flow
control, high-speed interconnection,
and
the implementation of all of these.)
- High-speed Digital Logic
Design
(This
includes the study of the fundamental
concepts of logic operations and
circuit level contributions
for
various logic schemes) |
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| ㆍEducation |
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| 2005.
8 Ph.D.
in EE, Korea Advanced Institute
of Science and Technology |
| Thesis:
Cost-Optimization and Chip Implemenation of On-Chip Network
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| 2001.
2 M.S.
in EE, Korea Advanced Institute
of Science and Technology |
| Thesis:
Performance Analysis of
Gigabit Ethernet Shared-Memory
Switch with Embedded DRAM |
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| 1999.
2 B.S.
in EE, Korea Advanced Institute
of Science and Technology |
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| 1995.
2 Daejeon
Science High School |
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| ㆍWork Experience |
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| 2012. 6 ~ Qualcomm, San Diego |
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| 2005.
12 ~ 2012. 6 Texas Instruments, Dallas |
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| ㆍPublications |
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International Journal Papers |
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Analysis
and Implementation of Practical
Cost-Effective Network-on-Chips
Se-Joong Lee, Kangmin
Lee and Hoi-Jun Yoo
IEEE
Design & Test of Computers
(Special Issue for NoC),
Sep.-Oct. 2005
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Packet-Switched
On-Chip Interconnection
Network for System-on-Chip
Applications
Se-Joong Lee, Kangmin
Lee, Seong-Jun Song and
Hoi-Jun Yoo
IEEE
Transactions on Circuits
and Systems II (TCAS), vol.
52, No. 6, pp. 308-312,
June 2005 |
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Race
Logic Architecture (RALA):
A Novel Logic Concept Using
the Race Scheme of Input
Variables
Se-Joong Lee and
Hoi-Jun Yoo
IEEE
Journal of Solid-State Circuit
(JSSC), Vol. 37, No. 2,
pp. 191-201, Feb. 2002
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International Conference
Papers |
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A
Network-on-Chip with 3Gbps/wire
Serialized On-chip Interconnect
Using Adaptive Control Schemes
Se-Joong Lee, Kwanho
Kim, Hyejung Kim, Namjun
Cho and Hoi-Jun Yoo
Design,
Automation and Test in Europe
(DATE), Mar. 2006 |
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Adaptive
Network-on-Chip with Wave-Front
Train Serialization Scheme
Se-Joong Lee, Kwanho
Kim, Hyejung Kim, Namjun
Cho and Hoi-Jun Yoo
IEEE
Symposium on VLSI (SOVC),
May 2005 |
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An
800MHz Star-Connected On-Chip
Network for Application
to Systems on a Chip
Se-Joong Lee, Seong-Jun
Song, Kangmin Lee, Jeong-Ho
Woo, Sung-Eun Kim, Byeong-Gyu
and Hoi-Jun Yoo
IEEE International Solid-State
Circuits Conference (ISSCC),
pp.468 - 469, 2003
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480ps
64-bit Race Logic Adder
Se-Joong Lee, Ramchan
Woo and Hoi-Jun Yoo
IEEE Symposium on VLSI Circuits
(SOVC), pp. 99-102, 2001 |
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A
Novel High Speed Low Power
Logic Family : Race Logic
Se-Joong Lee and
Hoi-Jun Yoo
IEEE European Solid-State
Circuit Conference (ESSCIRC),
pp. 420-423, Sept. 2000 |
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One
chip - low power Digital-TCXO
with Sub-ppm Accuracy
Se-Joong Lee and
Hoi-Jun Yoo
IEEE International Symposium
on Circuits and Systems
(ISCAS), vol. 3, pp. 17-20,
May 28, 2000
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