Home > Family > Alumni
Wang-Joo Lee Sungmin Park Se-Jeong Park Jae-Youl Lee Jun-Kyoung Kim
Sungdae Choi Sejong Oh Jeong-Ho Woo Jerald Yoo Joo-Young Kim
Seungjin Lee Joonsung Bae Jinwook Oh Taehwan Roh Junyoung Park
Kiseok Song Gyeonghoon Kim Injoon Hong Unsoo Ha Youchang Kim
Se-Jeong Park Yong-Ha Park Chi-Weon Yoon Ramchan Woo Se-Joong Lee
Kangmin Lee Sungdae Choi Ju-Ho Sohn Byeong-Gyu Nam Kyomin Sohn
Seong-Jun Song Jeong-Ho Woo Sunyoung Kim Donghyun Kim Namjun Cho
Kwanho Kim Hyejung Kim Jerald Yoo Joo-Young Kim Seungjin Lee
Long Yan Seulki Lee Joonsung Bae Jinwook Oh Taehwan Roh
Junyoung Park Kiseok Song Hyungwoo Lee Gyeonghoon Kim Sunjoo Hong
Hyunwoo Cho Injoon Hong Unsoo Ha Youchang Kim Kyuho Lee
Seongwook Park
Joo-Ho Lee Jae-Won Lim Jinho Han Jeonghoon Kook Jaeseo Lee
Sung-Eun Kim Jin Kyung Kim Min-Wuk Lee Jeabin Lee Yongsang Kim
Minsu Kim Binhee Kim Joonsoo Kwon Hyunki Kim



Yongha Park (¹Ú¿ëÇÏ)

   Ph.D.

¤ıResearch Interest
-  Mobile 3D Graphics
-  MPEG Video Post-Processor
-  Embedded Memory Logic Design
-  Low Power Design
¤ıContact Information
DSR, 1-1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, Korea
Tel: +82-31-209-9818
Email: yongha.park@samsung.com
¤ıPublications
- International Journal Papers
A Bit-Wise Read-Compare-Write Scheme for Low Power Read-Modify-Write Scheme
Yong-Ha Park, Sungdae Choi and Hoi-Jun Yoo
IEEE Electronics Letters , Vol. 38, No. 2, pp. 62-63, 17, Jan. 2002
Embedded DRAM (eDRAM) Power Energy Estimation Using Signal Swing-Based Analytical Model
Yong-Ha Park and Hoi-Jun Yoo
IEICE Transactions on Electronics, 2002
A 7.1GB/s Low-power Rendering Engine in 2D Array-embedded Memory Logic CMOS for Portable
Multimedia System

Yong-Ha Park, Seon-Ho Han, Jung-Hwan Lee and Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp. 944-955, June 2001
- International Conference Papers
Embedded DRAM (eDRAM) power-energy estimation for system-on-a-chip (SoC) applications
Yong-Ha Park, Jeonghoon Kook and Hoi-Jun Yoo
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002
7th Asia and South Pacific and the 15th International Conference on VLSI Design, pp. 625-630, 2002
Single Chip 3D Rendering Engine Integrating Embedded DRAM Frame Buffer and Hierarchical Octet Tree
(MOT) Array Processor with Bandwidth Amplification

Yong-Ha Park, Seon-Ho Han and Hoi-Jun Yoo
Design Automation Conference, 2001
Proceedings of the ASP-DAC 2001. Asia and South Pacific, pp.9-10,2001
A 7.1 GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS
Yong-Ha Park, Seon-Ho Han, Jung-Su Kim, Se-Joong Lee, Jeong-Hun Kook, Jae-Won Lim, Ramchan Woo,
Hoi-Jun Yoo, Jeong-Hwan Lee and Jay-Hyun Lee
IEEE International of Solid-State Circuits Conference, 2000
7.1 GB/sec bandwidth 3D rendering engine using the EML technology
Yong-Ha Park, Ramchan Woo, Sun-Ho Han, Jung-Su Kim, Se-Joong Lee, Jeong-Hun Kook,
Jae-Woon Lim and Hoi-Jun Yoo
6th International Conference on VLSI and CAD, pp. 277-280, 1999

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