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Wang-Joo Lee Sungmin Park Jae-Youl Lee Jun-Kyoung Kim Sungdae Choi
Sejong Oh Jeong-Ho Woo
Se-Jeong Park Yong-Ha Park Chi-Weon Yoon Ramchan Woo Se-Joong Lee
Kangmin Lee Sungdae Choi Ju-Ho Sohn Byeong-Gyu Nam Kyomin Sohn
Seong-Jun Song Jeong-Ho Woo Sunyoung Kim Donghyun Kim Namjun Cho
Kwanho Kim Hyejung Kim
Joo-Ho Lee Jae-Won Lim Jinho Han Jeonghoon Kook Jaeseo Lee
Sung-Eun Kim Jin Kyung Kim Min-Wuk Lee Jeabin Lee Yongsang Kim



Chi-Weon Yoon

   Ph.D.
¤ıContact Information

Flash Design Team.
ME Research Bldg.,Samsung Electronics Co., LTD,
Hwasung Campus, Banwol-dong, Hwasung-si, Kyonggi-do, Republic of Korea
Email: chiweon.yoon@samsung.com
¤ıResearch Interest
-  Flash Memory Design
¤ıPublications
- International Journal Papers
An 80/20-MHz 160-mW Multimedia Processor Integrated with Embedded DRAm, MPEG-4 Accelerator,
and 3-D Renderiing Engine for Mobile Applications
Chi-Weon Yoon, Ramchan Woo, Jeonghoon Kook, Se-Joong Lee, Kangmin Lee and Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits (JSSC), Vol.36, No.11, November, 2001
Low Power Motion Estimation and Motion Compensation Block IPs in MPEG-4 Video Codec Hardware
for Portable Applications
Chi-Weon Yoon and Hoi-Jun Yoo
The Institute of Electronics, Information and Communications Engineers (IEICE),
Tr.on Electronics Vol. E86-C, No.4, April 2003
- International Conference Papers
Low power MPEG-4 Video Codec Hardware for Portale Applications
Chi-Weon Yoon and Hoi-Jun Yoo
International Symposium on Low-Power and High-Speed Chips (Coolchips-V), pp.77-89, April 2002
A 80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM, MPEG-4 Accelerator,
and 3D Rendering Engine for Mobile Applications
Chi-Weon Yoon, Ramchan Woo, Jeonghoon Kook, Se-Joong Lee, Kangmin Lee, Young-Don Bae,
In-Cheol Park and Hoi-Jun Yoo
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 5~8. 2001, San Fancisco
Low Power Motion Compensation Block IP with emdedded DRAM Macro for Portable Multimedia
Applications
Chi-Weon Yoon, Jeonghoon Kook, Ramchan Woo, Se-Joong Lee, Kangmin Lee and Hoi-Jun Yoo
IEEE Symposium on VLSI Circuits (SOVC), June 12~14, 2001, Kyoto, Japan
A VPM(Virtual Pipelined Memory) Achitecture for a Fast Row-Cycle DRAM
Chi-Weon Yoon, Yon-Kyun Im, Seon-Ho Han, Hoi-Jun Yoo and Tae-Sung Jung
IEEE International Conference on VLSI and CAD (ICVC), pp. 388-391, 1999