Home > Research > Bio Microsystems > Research Projects

< Wearphone >


  Wearphone is a customizable low-power digital hearing aid chip according to the human external ear characteristics of the each individual user. It adopts the pre-fitting verification algorithm (PREVA) which enables the gain fitting and verification fast and accurate by two step fitting, coarse and fine. The ear canal modeling filter circuit (EMC) models the human external ear as a distributed LC filter for the fast coarse gain fitting. The fine fitting is performed by the conventional hearing loss test. For the low power operation, the multi-threshold preamplifier, the adaptive fitting digital signal processor (DSP) with the filter reuse technique and the gated successive approximation ADC are designed and embedded. The multi-threshold preamplifier has a dynamic range from 0.45V to 0.8V and dissipates 32µW from a single 0.9V supply. The fabricated chip achieves the peak SNR of 81dB in the overall system with 4.2µVrms of input-referred noise voltage. Its core area is 3.12 x 1.20 mm2 in a 0.18 um standard CMOS technology and it consumes only 107µW from a single 0.9V supply.

Ear Modeling Filter Circuit Design

Block Diagram of Overall Architecture & PAU

Chip Microphotograph

  - 0.18 µm 6M CMOS technology

  - 3.12 x 1.20mm2

  - 0.9V power supply

  - 107µW power consumption

Comparison of DHA Chip

Related Papers

  - ISSCC 07 [pdf]

  - SOVC 07 [pdf]

  - EMBC 07 [pdf]

  - CICC 07 [pdf]

  - JSSC 08 [pdf]

#1233, School of Electrical Engineering, KAIST, 291 Daehak-ro (373-1 Guseong-dong), Yuseong-gu,
Daejeon 34141, Republic of Korea / Tel. +82-42-350-8068 / Fax. +82-42-350-3410 / Mail: sslmaster@kaist.ac.kr
Copyright (C) 2017, SEMICONDUCTOR SYSTEM LAB., All Rights Reserved.