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   Real-time augmented reality (AR) is actively studied for the future user interface and experience in high-performance head-mounted display (HMD) systems. The small battery size and limited computing power of the current HMD, however, fail to implement the real-time markerless AR in the HMD. In this paper, we propose a real-time and low-power AR processor for advanced 3D-AR HMD applications. For the high throughput, the processor adopts task-level pipelined SIMD-PE clusters and a congestion-aware network-on-chip (NoC). Both of these two features exploit the high data-level parallelism (DLP) and task-level parallelism (TLP) with the pipelined multicore architecture. For the low power consumption, it employs a vocabulary forest accelerator and a mixed-mode support vector machine (SVM)-based DVFS control to reduce unnecessary external memory accesses and core activation. The proposed 4 mm x 8 mm HMD AR processor is fabricated using 65 nm CMOS technology for a battery-powered HMD platform with real-time AR operation. It consumes 381 mW average power and 778 mW peak power at 250 MHz operating frequency and 1.2 V supply voltage. It achieves 1.22 TOPS peak performance and 1.57 TOPS/W energy efficiency, which are, respectively, 3.58x and 1.18x higher than the state of the art.

Implementation results

Performance comparison



  - Task-level Pipelined Many-SIMD Architecture

  - Neural Network Scheduled 2D-mesh NoC

  - Vocabulary Forest Keypoint Matching Cluster

  - Mixed-mode SVM-based Dynamic Resource Management for DVFS

Related Papers

  - ISSCC 2014 [pdf]

  - COOLChips 2014 [pdf]

  - SOVC 2014 [pdf]

  - CICC 2014 [pdf]

  - ESSCIRC 2014 [pdf]

  - A-SSCC 2014 [pdf]

  - A-SSCC 2014 [pdf]

  - ICIT 2015 [pdf]

  - MICRO 2014 [pdf]

  - JSSC 2015 [pdf]

  - JSSC 2015 [pdf]

  - JSSC 2015 [pdf]

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