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Overview

  As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this paper, a configurable heterogeneous multi-core architecture with a dual-mode linear processor array and a cellular neural network on the network on chip platform is presented for real-time object recognition. The bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The cellular neural network is utilized to accelerate the visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into single instruction, multiple data (SIMD) or multiple-instruction-multiple-data modes to perform data-intensive image processing operations while exploiting pixel-level and feature-level parallelisms required for the attention-based object recognition.
  The algorithmí»s hybrid parallelization strategy on the proposed architecture is adopted to obtain maximum performance improvement. The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively parallel SIMD architecture at low hardware cost overhead. A prototype chip of the proposed architecture, fabricated in 0.13 ąým complementary metal-oxide semiconductor technology, achieves 22 frames/s real-time object recognition with less than 600 mW power consumption.



Implementation results



Performance comparison



Architecture



Features

a. SIMD/MIMD dual mode architecture
  - SIMD for massively parallel image processing
  - MIMD for object-level processing

b. Visual Attention Engine (VAE)
  - Compact 80x60 digital cellular neural networks for salient image region selection

c. Low latency Network-on-Chip
  - Adaptive switching for packet broad-casting
  - Image express channel for read latency reduction



Related Papers

  - ISSCC 08 [pdf] [Demo Video]

  - A-SSCC 08 [pdf]

  - ESSCIRC 08 [pdf]

  - JSSC 09 [pdf]

  - TCSVT 09 [pdf]



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