본문 바로가기
로그인

CHIP

Semiconductor System Lab

Through this homepage, we would like to share our sweats, pains,
excitements and experiences with you.

CHIP 2019

CHIP 목록
Image Title Specifications

2019

EIT

Technology

Chip Size

Power Supply

Function

Operating Frequency

Power Consumption

Released Date

65nm 1P8M CMOS Process

4.0 mm x 4.0 mm

3.3 V (Analog), 1.8V (Digital)

Electrical Impedance Tomography

10 kHz ~ 10 MHz

9.6 mW/Ch

July. 2019

2019

EIT

Technology

Chip Size

Power Supply

Function

Operating Frequency

Power Consumption

Released Date

65nm 1P8M CMOS Process

4.0 mm x 4.0 mm

3.3 V (Analog), 1.8V (Digital)

Electrical Impedance Tomography

10 kHz ~ 10 MHz

9.6 mW/Ch

July. 2019

2019

GANPU

Technology

Chip Size

Power Supply

Function

Operating Frequency

Power Consumption

Released Date

65 nm 1P8M CMOS Process

8.1 mm x 4.0 mm

0.70 V ~ 1.1 V

Generative Adversarial Network Inference & Training

Maximum 200 MHz

Maximum 647 mW

Jul. 2019

2019

GANPU

Technology

Chip Size

Power Supply

Function

Operating Frequency

Power Consumption

Released Date

65 nm 1P8M CMOS Process

8.1 mm x 4.0 mm

0.70 V ~ 1.1 V

Generative Adversarial Network Inference & Training

Maximum 200 MHz

Maximum 647 mW

Jul. 2019

Address#1233, School of Electrical Engineering, KAIST, 291 Daehak-ro (373-1 Guseong-dong), Yuseong-gu, Daejeon 34141, Republic of Korea
Tel +82-42-350-8068 Fax +82-42-350-3410E-mail sslmaster@kaist.ac.kr·© SSL. All Rights Reserved.·Design by NSTAR