- Multicore Processor Architecture
- Deep Learning Processor
- Intelligent 3D Vision SoC
2021. 3 ~ Ph.D. Student in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2021. 2 M.S. in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2019. 2 B.S. in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2014. 2 Gwangju Science High School
- International Journal Papers
A Low-Power Graph Convolutional Network Processor with Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices
Sangjin Kim, Sangyeob Kim, Juhyoung Lee, and Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems I (TCAS-I), Jan. 2022
- International Conference Papers
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Sangyeob Kim and Hoi-Jun Yoo
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), Apr. 2024
Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation
Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li and Hoi-Jun Yoo
IEEE Symposium on VLSI Circuits (S. VLSI), Apr. 2023
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, and Hoi-Jun Yoo
IEEE International Conference on Solid-State Circuits (ISSCC), Feb. 2023
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access
Sangjin Kim, Juhyoung Lee, Dongseok Im, and Hoi-jun Yoo
IEEE Symposium on High Performance Chips (HOT Chips), Aug. 2021
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access
Sangjin Kim, Juhyoung Lee, Dongseok Im, and Hoi-Jun Yoo
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices
Sangjin Kim, Sangyeob Kim, Juhyoung Lee, and Hoi-jun Yoo
IEEE International Symposium on Circuit and Systems (ISCAS), Oct. 2020
- Deep Learning & AI Algorithm
- Machine Learning based SoC Design
2023. 8 Ph.D. Student in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2020. 2 M.S. in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2018. 2 B.S. in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2014. 2 Kyongbuk Science High School
- International Journal Papers
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi and Hoi-Jun Yoo
TSUNAMI: Triple Sparsity-aware Ultra Energy-efficient Neural Network Training Accelerator with Multi-modal Iterative Pruning
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Donghyeon Han, Wooyoung Jo, and Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems I (TCAS-1), Jan. 2022
PNPU: An Energy-Efficient Deep-Neural-Network Learning Processor With Stochastic Coarse–Fine Level Weight Pruning and Adaptive Input/Output/Weight Zero Skipping
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinmook Lee, Wooyoung Jo, and Hoi-Jun Yoo
IEEE Solid-State Circuits Letters (SSCL), Dec. 2020
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, and Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems I (TCAS-1), Jan. 2020
- International Conference Papers
A Low-power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-device AI
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Nayeong Lee and Hoi-Jun Yoo
IEEE Symposium on High Performance Chips (HOT Chips), May. 2024
Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, and Hoi-Jun Yoo
IEEE International Symposium on Circuits and Systems (ISCAS), May. 2024
C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, and Hoi-Jun Yoo
COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, and Hoi-Jun Yoo
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), Mar. 2023
C-DNN: A 24.5-to-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-based Sparsity Generation
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, and Hoi-Jun Yoo
IEEE International Conference on Solid-State Circuits (ISSCC), Feb. 2023
SNPU: Always-on 63.2uW Face Recognition Spike Domain Convolutional Neural Network Processor with Spike Train Decomposition and Shift-and-Accumulation
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee, and Hoi-Jun Yoo
IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022
Neuro-CIM: A 310.4TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, and Hoi-Jun Yoo
IEEE Symposium on High Performance Chips (HOT Chips), Aug. 2022
Neuro-CIM: A 310.4TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, and Hoi-Jun Yoo
Symposium on VLSI Circuits (S. VLSI), Jun. 2022
PNPU: A 146.52TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinmook Lee, and Hoi-Jun Yoo
Symposium on VLSI Circuits (S. VLSI), Jun. 2020
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, and Hoi-Jun Yoo
IEEE International Symposium on Circuit and Systems (ISCAS), May. 2019
- Energy-efficient Deep Learning SoC Design
- Intelligent Vision System Development
2023. 8 Ph.D. Student in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2020. 2 M.S. in EE, Korea Advanced Insititue of Science and Technology (KAIST)
2018. 2 B.S. in EE, POSTECH
2014. 2 Jamsil High School
- International Journal Papers
A Mobile 3D Object Recognition Processor with Deep Learning-based Monocular Depth Estimation
Dongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, and Hoi-Jun Yoo
IEEE MICRO, Mar. 2023
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3-D Perception SoC
Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Junsu Lee, Wonhoon Park, Hankyul Kwon, and Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits (JSSC), 2022
A Pipelined Point Cloud based Neural Network Processor for 3D Vision with Large-scale Max Pooling Layer Prediction
Dongseok Im, Donghyeon Han, Sanghoon Kang, and Hoi-Jun Yoo
IEEE Journal of Solid-State Circuits (JSSC), Jun. 2021
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation
Dongseok Im, Donghyeon Han, Sungpill Choi, Sanghoon Kang, and Hoi-Jun Yoo
IEEE Transactions on Circuits and Systems I (TCAS-1), May. 2020
- International Conference Papers
LUTein: Dense-Sparse Bit-slice Architecture with Radix-4 LUT-based Slice-Tensor Processing Units
Dongseok Im, Hoi-Jun Yoo
IEEE International Symposium on High-Performance Computer Architecture (HPCA), Jan. 2024
Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation
Dongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, and Hoi-Jun Yoo
IEEE International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2023
DSPU: A 281.6mW Real-Time Deep Learning- Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip
Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, and Hoi-Jun Yoo
IEEE Symposium on High Performance Chips (HOT Chips), Aug. 2022
A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms
Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, and Hoi-Jun Yoo
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), Apr. 2022
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning- Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms
Dongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, Sanghoon Kang, Donghyeon Han, Jinsu Lee, and Hoi-Jun Yoo
International Solid-State Circuits Conference (ISSCC), Feb. 2022
A 4.45 ms Low-latency 3D Point-cloud-based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices
Dongseok Im, Sanghoon Kang, Donghyeon Han, Sungpill Choi, and Hoi-Jun Yoo
Symposium on VLSI Circuits (S. VLSI), Jun. 2020
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-time Image Segmentation on Mobile Devices
Dongseok Im, Donghyeon Han, Sungpill Choi, Sanghoon Kang, and Hoi-Jun Yoo
IEEE International Symposium on Circuit and Systems (ISCAS), May. 2019
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